DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 449

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SV52004-2.0
Transceiver Reset Signals
Transceiver Reset Controller Implementation
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52004-2.0
1
This chapter provides the recommended transceiver initialization and reset sequence
for Stratix
coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver
channel is initialized correctly. This is critical for reliable transceiver operations after
the initial power-up and for re-establishing the transceiver link.
Table 3–1
each signal.
Table 3–1. Transceiver Reset Signals
The transceiver reset sequence controller is automatically implemented as part of the
PHY IP core in each transceiver configuration. This approach simplifies
transceiver-based design development because the embedded reset sequence
controller ensures reliable transceiver link initialization.
There is only one reset controller for all the channels in a PHY IP instance.
pll_powerdown
tx_digitalreset
rx_analogreset
rx_digitalreset
Note to
(1) These are internal signal names that could be different from the PHY IP or Custom PHY register names.
Internal Signal Name
Table
lists the transceiver reset signals and the transceiver circuitry impacted by
®
3–1:
V devices. The recommended reset sequence ensures that the physical
Resets the transmitter PLL when asserted high
Resets all blocks in the transmitter PCS when asserted high
Resets the receiver CDR when asserted high
Resets all blocks in the receiver PCS when asserted high
(Note 1)
3. Transceiver Reset Control in
Impacted Transceiver Circuitry
Stratix V Devices
Subscribe