DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 235

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
LVDS Interface with the Use External PLL Option Enabled
LVDS Interface with the Use External PLL Option Enabled
May 2011 Altera Corporation
LVDS Direct Loopback Mode
1
1
1
You can use every LVDS channel in soft-CDR mode and drive the FPGA fabric using
the PCLK network in the Stratix V device family. The rx_dpa_locked signal is not
valid in soft-CDR mode because the DPA continuously changes its phase to track
PPM differences between the upstream transmitter and the local receiver input
reference clocks. The parallel clock rx_outclock, generated by the left and right PLLs,
is also forwarded to the FPGA fabric.
The Stratix V device family supports direct loopback mode for the LVDS driver and
receiver pairs within the same LVDS module only.
input and output buffer from an I/O pair from the same module. LVDS direct
loopback mode allows you to verify the LVDS driver and receiver pair by checking
the incoming LVDS data from the true LVDS input buffer into the true LVDS output
buffer.
Figure 6–20. LVDS Direct Loopback Path
Note to
(1) The R
The Quartus II software allows two option settings for LVDS direct loopback mode in
the assignment editor: On and Off.
This option is only available for true differential I/O standards only.
This option can be applied on the LVDS output pair that is already being used in the
design. Turning the LVDS direct loopback mode option to On overrides the
connection from core with the signal from the true differential input buffer in the
same I/O module. You can disable this option after verifying the LVDS driver receiver
pair. Turn the LVDS direct loopback mode option to Off and recompile your design.
The ALTLVDS MegaWizard Plug-In Manager provides an option for implementing
the LVDS interface with the Use External PLL option. With this option enabled you
can control the PLL settings, such as dynamically reconfiguring the PLL to support
different data rates, dynamic phase shift, and other settings. You also must instantiate
an ALTPLL megafunction to generate the various clock and load enable signals.
The ALTLVDS Use External PLL option will only be available in future Quartus II
software releases.
Figure
D
value is pending characterization.
6–20:
Rx1[p] Rx1[n]
LVDS
In
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(Note 1)
R
Loopback
D
= 100 Ω
Tx1[p] Tx1[n]
LVDS
Out
Figure 6–20
shows the true LVDS
6–21