DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 396

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–24
Stratix V Device Handbook Volume 3: Transceivers
f
Receiver Byte Reversal in Custom Double-Width Configurations
The MSByte and LSByte of the input data to the transmitter may be erroneously
swapped. The receiver byte reversal feature is available to correct this situation.
Figure 1–17
Figure 1–17. Receiver Byte Reversal Feature
Rate Match (Clock Rate Compensation) FIFO
In asynchronous systems, you can use independent reference clocks to clock the
upstream transmitter and local receiver. Frequency differences in the order of a few
hundred PPM can corrupt the data when latching from the recovered clock domain
(the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain.
The rate match (clock rate compensation) FIFO compensates for small clock frequency
differences between the upstream transmitter and the local receiver clocks by
inserting or removing SKP symbols or ordered sets from the inter-packet gap (IPG) or
idle streams. It deletes SKP symbols or ordered sets when the upstream transmitter
reference clock frequency is higher than the local receiver reference clock frequency. It
inserts SKP symbols or ordered-sets when the local receiver reference clock frequency
is higher than the upstream transmitter reference clock frequency.
For more information about how to use the rate match FIFO with PCIe, XAUI, and
Custom protocols, refer to the
chapter.
Byte Order Enable
shows the receiver byte reversal feature.
MSByte
MSByte
MSByte
LSByte
LSByte
LSByte
01
00
00
01
xx
xx
Transceiver Protocol Configurations in Stratix V Devices
03
02
02
03
xx
xx
05
04
04
05
07
06
06
07
07
06
Chapter 1: Transceiver Architecture in Stratix V Devices
09
08
08
09
09
08
0B
0A
0A
0B
0B
0A
Actual Data without
Byte Order Enabled
Corrected Data Out
Expected Data Out
of the Word Aligner
of the Word Aligner
May 2011 Altera Corporation
Standard PCS Architecture