DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 291

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Fast Passive Parallel Configuration
Figure 9–2. Multi-Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of
Configuration Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. V
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin.
(3) The MSEL pin settings vary for different data width and POR delay. To connect MSEL, refer to
(4)
May 2011 Altera Corporation
specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V
If you use FPP ×8, use DATA[7..0]. If you use FPP ×16, use DATA[15..0]. All devices in the chain must have the same data width.
Figure
FPP Multi-Device Configuration
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
9–2:
1
Memory
For FPP multi-device configuration, you can configure all devices with different sets
of configuration data (multiple SRAM object files [.sofs]) or with the same
configuration data (single .sof). In both cases, the nCONFIG, nSTATUS, DCLK, DATA[], and
CONF_DONE pins are connected to every device in the chain. Ensure that the DCLK and
data line are buffered for every fourth device. This ensures the signal integrity and
prevents clock skew problems.
Because all device’s CONF_DONE and nSTATUS pins are tied together, all devices initialize
and enter user mode at the same time. If any device detects an error, configuration
stops for the entire chain and you must reconfigure all devices. For example, if the
first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low.
This behavior is similar to a single device detecting an error.
For FPP multi-device configuration, all devices in the chain must have the same data
width. If you are using FPP ×32, all devices in the chain must use FPP ×32
configuration scheme. If you are using FPP ×8, you can use the Stratix V device with
other FPGA devices that support FPP ×8.
Figure 9–2
both devices receive a different set of configuration data (multiple .sofs).
In
configuration chain, its nCEO pin drives low to activate the second device’s nCE pin,
which prompts the second device to begin configuration. The second device in the
chain begins configuration in one clock cycle; therefore, the transfer of data to the
second device is transparent to the MAX II device or microprocessor.
Figure
V
10 kΩ
CCPGM
9–2, after the first device completes configuration in a multi-device
shows how to configure multiple devices using a MAX II device when
(1) V
CCPGM
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
DATA[31..0]
nCONFIG
DCLK
Stratix V Device 1
MSEL[4..0]
(4)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
nCEO
(2)
Table 9–4 on page
CCPGM
must be high enough to meet the V
DATA[31..0]
9–7.
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Stratix V Device 2
MSEL[4..0]
(4)
nCEO
CCPGM
.
N.C.
(2)
9–11
IH