DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 330

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–50
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
The application-not-factory (AnF) bit indicates whether the current configuration
loaded in the Stratix V device is the factory configuration or an application
configuration. This bit is set low by the remote system upgrade circuitry when an
error condition causes a fall-back to the factory configuration. When the AnF bit is
high, the control register restricts the access to only read operations and enables the
watchdog timer. The factory configuration design must set this bit high (1'b1) when
updating the contents of the update register with the application page address and
watchdog timer settings.
Table 9–17
Table 9–17. Remote System Upgrade Control Register Contents
Status Register
The status register specifies the reconfiguration trigger condition.
the status register content. The following list defines each bit:
■
■
■
■
■
Figure 9–31
the bit positions in a 5-bit register.
Figure 9–31. Remote System Upgrade Status Register
Note to
(1) After the device exits POR and powers-up, the status register content is 5'b00000.
AnF
PGM[23..0]
Wd_en
Wd_timer[11..0]
Notes to
(1) Factory configuration designs must set the AnF bit to 1'b1 before triggering the reconfiguration to application
(2) This is the default value of the control register bit after the device exits POR and during reconfiguration back to the
Bit 0—CRC error during application configuration
Bit 1—nSTATUS assertion by an external device due to an error
Bit 2—Stratix V device logic array triggered a reconfiguration cycle, possibly after
downloading a new application configuration image
Bit 3—external configuration reset (nCONFIG) assertion
Bit 4—user watchdog timer time-out
Control Register Bit
configuration image.
factory configuration image after reconfiguration trigger conditions.
(1)
Figure
Table
lists the remote system upgrade control register contents.
9–31:
shows the contents of the status register. The numbers in the figure show
9–17:
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Wd
4
nCONFIG
12'b000000000000
3
24'b0×000000
Value
1'b0
1'b0
Core_nCONFIG
(2)
2
(Note 1)
nSTATUS
Application not factory
AS configuration start address
(StAdd[23..0])
User watchdog timer enable bit
User watchdog time-out value (most
significant 12 bits of 29-bit count
value: {Wd_timer[11..0], 17'b0})
1
CRC
0
May 2011 Altera Corporation
Definition
Figure 9–31
Remote System Upgrades
shows