DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 9

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Stratix V Features Summary
Stratix V Features Summary
June 2011 Altera Corporation
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Technology
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Low-power serial transceivers
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General purpose I/Os
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Embedded HardCopy Block
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Embedded transceiver hard IP
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Power Management
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High-performance core fabric
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28-nm TSMC process technology
0.85-V core voltage
28-Gbps transceivers on Stratix V GT devices
Electronic dispersion compensation (EDC) for XFP,
SFP+, QSFP, CFP optical module support
Adaptive linear and decision feedback equalization
600 Mbps to 14.1 Gbps backplane capability
Transmit pre-emphasis and de-emphasis
Dynamic reconfiguration of individual channels
On-chip instrumentation (EyeQ non-intrusive data eye
monitoring)
1.4-Gbps LVDS
1,066-MHz/1,600-Mbps external memory interface
On-chip termination (OCT)
1.2-V to 3.3-V interfacing for all Stratix V devices
PCIe Gen 3/2/1 complete protocol stack, ×1/×2/×4/×8
end point and root port
40G/100G Ethernet physical coding sublayer (PCS)
Interlaken PCS
Gigabit Ethernet (GbE) and XAUI PCS
10G Ethernet PCS
Serial RapidIO (SRIO) PCS
Common Public Radio Interface (CPRI) PCS
Gigabit Passive Optical Networking (GPON) PCS
Programmable Power Technology
Quartus II integrated PowerPlay Power Analysis
Enhanced ALM with four registers
Improved routing architecture reduces congestion and
improves compile times
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Embedded memory blocks
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Variable precision DSP blocks
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Fractional PLLs
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Clock networks
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Device Configuration
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High-performance packaging
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HardCopy V migration
M20K: 20-Kbit with hard error correction code (ECC)
MLAB: 640-bit
Up to 500 MHz performance
Natively support signal processing with precision
ranging from 9×9 up to 54×54
New native 27×27 multiply mode
64-bit accumulator and cascade for systolic finite
impulse responses (FIRs)
Embedded internal coefficient memory
Pre-adder/subtractor improves efficiency
Increased number of outputs allows more independent
multipliers
Fractional mode with third-order delta-sigma
modulation
Integer mode
Precision clock synthesis, clock delay compensation,
and zero delay buffering
717-MHz fabric clocking
Global, quadrant, and peripheral clock networks
Unused clock networks can be powered down to
reduce dynamic power
Serial and parallel flash interface
Enhanced advanced encryption standard (AES) design
security features
Tamper protection
Partial and dynamic reconfiguration
Configuration via Protocol (CvP)
Multiple device densities with identical package
footprints enables seamless migration between
different FPGA densities
FBGA packaging with on-package decoupling
capacitors
Lead and RoHS-compliant lead-free options
Stratix V Device Handbook
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