DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 158

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–18
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Table 4–4
Table 4–4. PLL Features for Stratix V Devices —Preliminary
Integer PLL
Fractional PLL
C output counters
M, N, C counter sizes
Dedicated external clock outputs
Clock input pins
External feedback input pin
Spread-spectrum input clock tracking
Source synchronous compensation
Direct compensation
Normal compensation
Zero delay buffer (ZDB) compensation
External feedback compensation
LVDS compensation
VCO output drives the DPA clock
Phase shift resolution
Programmable duty cycle
Notes to
(1) Provided input clock jitter is within input jitter tolerance specifications.
(2) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
degree increments, the Stratix V device can shift all output frequencies in increments of at least 45
increments are possible depending on the frequency and divide parameters.
Table
lists the features of PLLs in Stratix V devices.
4–4:
Feature
Chapter 4: Clock Networks and PLLs in Stratix V Devices
4 single-ended or 2 single-ended and
4 single-ended or 4 differential
Single-ended or differential
78.125 ps
1 differential
Stratix V
1 to 512
Yes
May 2011 Altera Corporation
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
18
(1)
(2)
°
. Smaller degree
Stratix V PLLs