DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 187
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 187 of 530
- Download datasheet (16Mb)
Chapter 5: I/O Features in Stratix V Devices
I/O Structure
May 2011 Altera Corporation
Current Strength
1
The output buffer for each Stratix V device I/O pin has programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL I/O standards have
several levels of current strength that you can control.
programmable current strength settings for Stratix V devices.
Table 5–9. Programmable Current Strength Settings
Altera recommends performing IBIS or SPICE simulations to determine the best
current strength setting for your specific application.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
SSTL-12
SSTL-15
SSTL-125
SSTL-135
HSUL-12
Notes to
(1) The 3.3-V LVTTL and 3.3-V LVCMOS I/O standards are supported using V
(2) The current strength is represented by the driver impedance value (). Only R
(3) Pending silicon characterization.
Table
I/O Standard
(1)
5–9:
(1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
34, 40, 48, 60, 80 (2),
I
OH
34, 40, 25, 50 (2),
40, 60, 240 (2),
/ I
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
34, 40 (2),
34, 40 (2),
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
8, 6, 4, 2
12, 10, 8
Setting
16
16
16
16
16
16
(3)
(3)
Table 5–9
(3)
(3)
CCIO
(3)
S
and V
OCT with calibration is supported.
lists the
CCPD
at 3.0 V.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5–11
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: