DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 438

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–22
FPGA Fabric-Transceiver Interface Clocking
Table 2–4. FPGA Fabric-Transceiver Interface Clocks
Stratix V Device Handbook Volume 3: Transceivers
pll_ref_clk
tx_clkout
rx_clkout
tx_coreclkin
rx_coreclkin
fixed_clk
Clock Name
f
Input reference clock used for clocking logic in the
FPGA fabric
Clock forwarded by the transceiver for clocking the
transceiver datapath interface
Clock forwarded by the receiver for clocking the
receiver datapath interface
User-selected clock for clocking the transmitter
datapath interface
User-selected clock for clocking the receiver
datapath interface
PCIe receiver detect clock
For more information about the clocking scheme used in different configurations,
refer to the
Transceiver Configuration Datapath in Stratix V Devices
The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA
fabric to the transceiver blocks and clock signals from the transceiver blocks to the
FPGA fabric. These clock resources use the clock networks in the FPGA core,
including the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks.
The FPGA fabric-transceiver interface clocks can be subdivided into the following
three categories:
■
■
■
Table 2–4
Input reference clocks—Refer to
input reference clock can be an FPGA fabric-transceiver interface clock when it is
also forwarded to the FPGA fabric to clock logic in the FPGA fabric.
Transceiver datapath interface clocks—Used to transfer data, control, and status
signals between the FPGA fabric and the transceiver channels. The transceiver
channel forwards the tx_clkout signal to the FPGA fabric to clock the data and
control signals into the transmitter. The transceiver channel also forwards the
recovered rx_clkout clock (in configurations without the rate matcher) or the
tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to
clock the data and status signals from the receiver into the FPGA fabric.
Other transceiver clocks—The following transceiver clocks form a part of the
FPGA fabric-transceiver interface clocks:
■
■
mgmt_clk—Avalon-MM interface clock used for controlling the transceivers,
dynamic reconfiguration, and calibration
fixed_clk—125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect
circuitry
lists the FPGA fabric-transceiver interface clocks.
Clock Description
Transceiver Protocol Configurations in Stratix V Devices
(Note 1)
“Input Reference Clock Sources” on page
(Part 1 of 2)
Transceiver-to-FPGA fabric
Transceiver-to-FPGA fabric
Transceiver-to-FPGA fabric
FPGA fabric-to-transceiver
FPGA fabric-to-transceiver
FPGA fabric-to-transceiver
Interface Direction
Chapter 2: Transceiver Clocking in Stratix V Devices
chapters.
FPGA Fabric-Transceiver Interface Clocking
May 2011 Altera Corporation
and
Resource Utilization
FPGA Fabric Clock
GCLK, RCLK, PCLK
GCLK, RCLK, PCLK
GCLK, RCLK, PCLK
GCLK, RCLK, PCLK
GCLK, RCLK, PCLK
GCLK, RCLK, PCLK
Custom
2–2. The