DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 477

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
Figure 4–13. PCIe Reverse Parallel Loopback Mode Datapath (Grayed-out Blocks are Inactive)
May 2011 Altera Corporation
Fabric
FPGA
f
f
1
For more information about the rate match FIFO operation in a PCIe configuration,
refer to the
For more information about status signals and registers for the rate match FIFO, refer
to the PCI Express PIPE PHY IP Core chapter in the
Guide.
PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1 and Gen2 data rates. As shown in
through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer.
It is then looped back to the transmitter serializer and transmitted out through the
transmitter buffer. The received data is also available to the FPGA fabric through the
port. This loopback mode is compliant with the PCIe specification 2.0. Stratix V
devices provide an input signal to enable this loopback mode.
This is the only loopback option supported in PIPE configurations.
Transceiver Architecture in Stratix V Devices
Receiver PCS
Transmitter PCS
Figure
4–13, the received serial data passes
Stratix V Device Handbook Volume 3: Transceivers
Altera Transceiver PHY IP Core User
chapter.
Reverse Parallel
Loopback Path
Transmitter PMA
Receiver PMA
4–21