DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 442

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–26
Stratix V Device Handbook Volume 3: Transceivers
1
Figure 2–19
clocked by the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the
central clock divider of channel 1 or 4 in a transceiver bank.
Figure 2–19. Transmitter Datapath Interface Clocking for Three Bonded Channels
User-Selected Transmitter Datapath Interface Clock
Multiple transmitter channels that are non-bonded lead to high utilization of GCLK,
RCLK, and PCLK resources (one clock resource per channel as shown in
You can significantly reduce GCLK, RCLK, and PCLK resource use for transmitter
datapath clocks if the transmitter channels are identical.
Identical transmitter channels are defined as channels that have the same input
reference clock source, the same transmit PLL configuration, and the same transmitter
PMA and PCS configuration. Identical transmitter channels may have different
analog settings, such as transmitter voltage output differential (V
common mode voltage (V
Data and Control Logic
Data and Control Logic
Data and Control Logic
Channel 1 Transmitter
Channel 0 Transmitter
Channel 2 Transmitter
shows the transmitter datapath interface of three bonded channels
FPGA Fabric
tx_coreclkin[1]
tx_coreclkin[0]
tx_coreclkin[2]
CM
), or pre-emphasis setting.
Transmitter Data
Transmitter Data
Transmitter Data
tx_clkout[0]
Chapter 2: Transceiver Clocking in Stratix V Devices
Compensation
Compensation
Compensation
FPGA Fabric-Transceiver Interface Clocking
Phase
Phase
Phase
FIFO
FIFO
FIFO
TX
TX
TX
May 2011 Altera Corporation
Parallel Clock
Parallel Clock
Parallel Clock
OD
), transmitter
Transmitter Data
Transmitter Data
Transmitter Data
Figure
Channel 2
Channel 1
Channel 0
2–18).