DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 231

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Differential Receiver
Figure 6–16. Stratix V Deserializer Bypass
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
May 2011 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
6–16:
2
Deserializer
You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by
using the Quartus II software. You can bypass the Stratix V deserializer in the
Quartus II MegaWizard Plug-In Manager to support DDR (x2) or SDR (x1) operations,
as shown
deserializer is bypassed. The IOE contains two data input registers that can operate in
DDR or SDR mode.
(LOAD_EN, diffioclk)
IOE supports SDR, DDR, or
2
Non-Registered Datapath
Deserializer
Deser
Deserializ
Figure
DOUT DIN
ializer
er
6–16. The DPA and data realignment circuit cannot be used when the
IOE
(Note
2
Fractional PLL
3
1), (2),
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LO
L L
LVDS_diffioclk,
L L
rx_outclk)
diffioclk
AD_EN,
(3)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
3
(DPA_LO
DPA_diffioclk,
P P
rx_divfwdclk)
P P
AD_EN,
Retimed
DPA Circuitr
DPA Cloc
Data
P P
P P
k
DIN
y
+
rx_in
6–17