DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 510

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–8
Standard PCS Custom and Low Latency Configurations
Stratix V Device Handbook Volume 3: Transceivers
Merging Instances
You can merge transmitter and receiver instances with the different 10G PCS datapath
configurations in the same 10 Gbps physical channel. For example, the Quartus II
software allows you to create the two following instances and place them in the same
physical transceiver channel:
■
■
You cannot merge a transmitter instance and receiver instance (1 channel instance)
using different PCS blocks (10G PCS and standard PCS) within the same physical
transceiver channel.
Transceiver Channel Placement Guidelines
Stratix V devices allow the placement of up to five channels in 10G custom
configurations (same data rate) within the same transceiver bank.
supported channel placement scenario.
Figure 5–7. Channel Placement Guidelines in 10G Custom Configurations
Note to
(1) All channels shown in
With custom configurations using the standard PCS, you can select which blocks to
use and the data width by creating user-defined configurations. You can also
implement protocols such as SONET, Fibre Channel, or SerialLite II by customizing
the transceiver PCS configuration. Low latency configurations bypass much of the
standard PCS, allowing for more design control in the FPGA fabric. This section
discusses how to use the custom and Low Latency PHY IP core with the standard
PCS.
10G Custom Configuration Ch4 (1)
10G Custom Configuration Ch3 (1)
10G Custom Configuration Ch2 (1)
10G Custom Configuration Ch1 (1)
10G Custom Configuration Ch0 (1)
Transmitter only instance with a 40-bit FPGA fabric interface
Receiver only instance with a 64-bit FPGA fabric interface
Figure
CMU PLL
5–7:
Figure 5–7
are assumed to contain a transmitter and receiver.
×1 Transmitter
Clock Line
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
10G Custom Configuration Ch4 (1)
10G Custom Configuration Ch3 (1)
10G Custom Configuration Ch2 (1)
10G Custom Configuration Ch1 (1)
10G Custom Configuration Ch0 (1)
Standard PCS Custom and Low Latency Configurations
CMU PLL
May 2011 Altera Corporation
Figure 5–7
×1 Transmitter
shows a
Clock Line