DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 414

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–42
Bonded Configuration
Stratix V Device Handbook Volume 3: Transceivers
f
Figure 1–39
10GBASE-R configurations.
Figure 1–39. Transmitter Gear Box
In addition to providing bus width adaptation, the transmitter gear box provides the
transmitter bit reversal and bit-slip features.
Transmitter Bit Reversal
The transmitter gear box also provides the ability to reverse the order of transmitted
bits. By default, the transmitter first sends out the LSB of a word. Some protocols,
such as Interlaken, require that the MSB of a word (bit 66 in a word [66:0]) is
transmitted first. When you enable the transmitter bit reversal feature, the parallel
input to the gear box is swapped and the MSB is sent out first. The Quartus II software
automatically sets the bit reversal feature for the Interlaken configuration.
Transmitter Bit-Slip
The transmitter bit-slip feature allows you to compensate for the channel-to-channel
skew between multiple transmitter channels by slipping the data sent to the PMA.
The maximum number of bits slipped is controlled from the FPGA fabric and is equal
to the width of the PMA-PCS minus 1. This feature is supported only in 10G custom
configurations.
For more information, refer to the
Transceiver Custom Configurations in Stratix V Devices chapter.
The high-speed serial clock and low-speed parallel clock skew between channels and
unequal latency in the transmitter phase compensation FIFO contribute to transmitter
channel-to-channel skew. Bonded transmitter datapath clocking provides low
channel-to-channel skew when compared with non-bonded channel configurations.
■
Bonded channel configurations—the serial clock and parallel clock for all bonded
channels are generated by the transmit PLL and central clock divider, resulting in
lower channel-to-channel clock skew.
The transmitter phase compensation FIFO in all bonded channels share common
pointers and control logic generated in the central clock divider, resulting in equal
latency in the transmitter phase compensation FIFO of all bonded channels. The
lower transceiver clock skew and equal latency in the transmitter phase
compensation FIFOs in all channels provide lower channel-to-channel skew in
bonded channel configurations.
66-Bit in 10GBASE-R
67-Bit in Interlaken
shows the transmitter gear box with data widths for the Interlaken and
data_valid
TX Gear Box
Reversal
10G Low Latency Configuration
TX
Bit
Chapter 1: Transceiver Architecture in Stratix V Devices
40-Bit Data to Transceiver Channel PMA
May 2011 Altera Corporation
section in the
Bonded Configuration