DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 209

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
May 2011 Altera Corporation
1
Figure 5–20
Figure 5–20. Emulated RSDS I/O Standard Termination
Note to
(1) The R
A resistor network is required to attenuate the output-voltage swing to meet RSDS
specifications. You can modify the three-resistor network values to reduce power or
improve the noise margin. The resistor values chosen must satisfy
Equation 5–1.
Altera recommends performing additional simulations using IBIS or SPICE models to
validate that custom resistor values meet the RSDS I/O standard requirements.
Termination
Termination
On-Board
External
Figure
OCT
S
and R
5–20:
shows the emulated RSDS I/O standard termination.
P
values
are pending characterization.
Transmitter
Transmitter
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
------------------- -
R s
R s
External Resistor
External Resistor
Three-Resistor Network (RSDS_E_3R)
≤
≤

+
1 inch
1 inch
R
R
R
R
R p
------ -
R p
------ -
S
S
S
S
2
2
=
50
R
R
P
P
(Note 1)
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100 Ω
Stratix V OCT
Equation
Receiver
Receiver
5–1.
5–33