DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 185

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
I/O Structure
I/O Structure
Figure 5–2. IOE Structure for Stratix V Devices
Notes to
(1) The D3_0 and D3_1 delays have the same available settings in the Quartus II software.
(2) One dynamic OCT control is available per DQ/DQS group.
May 2011 Altera Corporation
From Core
DQS
CQn
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
clkin
Figure
4
5–2:
4
D4 Delay
2
Rate Block
Half Data
Rate Block
Half Data
The I/O elements (IOEs) in Stratix V devices contain a bidirectional I/O buffer and
I/O registers to support a complete embedded bidirectional SDR or DDR transfer. The
IOEs are located in I/O blocks around the periphery of the Stratix V device.
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output
enable, OE path for handling the OE signal to the output buffer. These registers allow
faster source-synchronous register-to-register transfers and resynchronization. The
input path consists of the DDR input registers, alignment and synchronization
registers, and half data rate blocks; you can bypass each block in the input path. The
input path uses the deskew delay to adjust the input register clock delay across
process, voltage, and temperature (PVT) variations.
The output and OE paths are divided into the output or OE registers, alignment
registers, and half data rate blocks. You can bypass each block of the output and OE
paths.
Figure 5–2
Delay
D3_1
Rate Block
Half Data
Alignment
Registers
Alignment
Registers
shows the Stratix V IOE structure.
Deskew Delay
Synchronization
Output Register
Output Register
OE Register
OE Register
Alignment and
D
D
D
D
Registers
PRN
PRN
PRN
PRN
Q
Q
Q
Q
(Note
1),
D3_0
Delay
Delay
D1
(2)
Input Register
Input Register
D
D
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
PRN
PRN
D5, D6
Delay
Q
Q
D2 Delay
Programmable
Input Register
Strength and
D
Slew Rate
Current
Control
PRN
Q
Open Drain
D5, D6
Delay
Output Buffer
Input Buffer
DQS Logic Block
V CCIO
D5_OCT
Dynamic OCT Control (2)
Pull-Up Resistor
Programmable
Termination
Calibration
From OCT
On-Chip
Bus-Hold
Block
D6_OCT
Circuit
5–9