DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 422

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–6
Stratix V Device Handbook Volume 3: Transceivers
1
1
Transmitter Clock Network Architecture
The transmitter clock network consists of the two types of dedicated clocking
resources:
■
■
The Quartus II software performs the clock routing related to the transmitter clock
network based on the transceiver configuration selected.
×1 clock lines are used for non-bonded configurations and only route the serial clock
lines from the transmit PLL to the clock divider of the transceiver channels.
shows the ×1 clock lines. The following resources can drive the ×1 clock lines:
■
■
The ×1 clock lines can drive the local clock divider and central clock divider of any
channel within a transceiver bank.
The channel PLL can be used to drive the local clock divider or the central clock
divider of its own channel if it is configured as a CMU PLL. However, you will not be
able to use the channel PLL as a CDR. Without a CDR, you can only use the channel as
a transmitter channel.
Non-bonded configurations
■
Bonded configurations
■
■
Channel PLLs (configured as a CMU PLL) of channel 1 and 4 in a transceiver bank
ATX PLLs in the transceiver bank
×1 clock lines
×6 clock lines
×N clock lines
Chapter 2: Transceiver Clocking in Stratix V Devices
May 2011 Altera Corporation
Internal Clocking
Figure 2–6