DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 521
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Standard PCS Custom and Low Latency Configurations
May 2011 Altera Corporation
f
Figure 5–17
PMA-PCS interface width. The blocks shown as “Disabled” are not used, but incur
latency. The blocks shown as “Bypassed” are not used and do not incur any latency.
The maximum frequencies shown in
For more information about the maximum data rate for a certain speed grade, refer to
the
Figure 5–17. Standard PCS Low Latency 20-Bit PMA-PCS Interface Width
DC and Switching Characteristics for Stratix V Devices
Data Rate (Gbps)
Number of Bonded Channels
Word Aligner (Pattern Length)
Rate Match FIFO
8B/10B Encoder/Decoder
Byte Serializer/Deserializer
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
shows the available options for the standard PCS low latency 20-bit
Figure 5–17
are for the fastest devices.
Stratix V Device Handbook Volume 3: Transceivers
Bypassed Bypassed
Disabled Enabled
20-Bit
282.5
1.0 -
5.65
50 -
Bypassed
Bypassed
Bypassed
Up to ×5
1.0-8.5
chapter.
40-Bit
212.5
25 -
1.0 -
8.5
5–19
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