DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 505

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: Transceiver Custom Configurations in Stratix V Devices
10G Low Latency Configuration
Figure 5–2. Options for 10G Low Latency Configuration
Notes to
(1) For the limits of all speed grades, refer to the “Transceiver Specifications for Stratix V GX and GS Devices” table in the
(2) You must generate an rx_coreclk with the specified frequency whenever the gear box is enabled.
May 2011 Altera Corporation
Characteristics for Stratix V Devices
Figure
5–2:
f
Transceiver PHY IP
Data Rate (Gbps)
Number of Bonded Channels
PCS-PMA Interface Width (Bits)
Tx Bit Slip
Gear Box
Block Synchronizer
Disparity Generator, Checker
Scrambler, Descrambler
64B/66B Encoder/Decoder
BER Monitor
Frame Generator, Synchronizer
TX FIFO, RX FIFO
FPGA Fabric-to-Transceiver
Interface Width
CRC32 Generator, Checker
Data Rate (Gbps)
Max FPGA Fabric-to-Transceiver
Interface Frequency (MHz) (2)
For the limits for all speed grades, refer to the
Stratix V Devices
chapter.
chapter.
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Enabled
Enabled
2 - 12.5
195.31
64-Bit
Optional
(Note 1)
32
8.5 - 9.04
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Disabled
Enabled
282.5
32-Bit
Custom PHY IP
2.0 - 12.5 Gbps
None
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Optional
Enabled
Enabled
151.52
DC and Switching Characteristics for
66-Bit
2 - 10
Stratix V Device Handbook Volume 3: Transceivers
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Disabled
Enabled
Enabled
2 - 12.5
50-Bit
250
40
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Disabled
Disabled
Enabled
2 -11.3
282.5
40-Bit
DC and Switching
5–3