DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 233

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Differential Receiver
Figure 6–18. Receiver Datapath in DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
May 2011 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
6–18:
10
DPA Mode
Figure 6–18
in
best possible clock (DPA_diffioclk) from the eight fast clocks sent by the fractional
PLL. This serial DPA_diffioclk clock is used for writing the serial data into the
synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from
the synchronizer. The same LVDS_diffioclk clock is used in data realignment and
deserializer blocks.
IOE Supports SDR, DDR, or Non-Registered Datapath
“Receiver Hardware Blocks” on page 6–14
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the DPA mode datapath, where all the hardware blocks mentioned
IOE
2
Fractional PLL
3
(Note
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
1), (2),
diffioclk
(3)
rx_inclock
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
are active. The DPA block chooses the
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
Data
DPA Clock
DPA Circuitry
DIN
+
LVDS Clock Domain
DPA Clock Domain
rx_in
6–19