DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 191

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
May 2011 Altera Corporation
1
Stratix V devices support OCT in all I/O banks. You can use R
same I/O bank for different I/O standards if they use the same V
You can independently configure each I/O in an I/O bank to support R
programmable current strength, or R
You cannot configure both the R
same I/O buffer.
The Stratix V OCT calibration process uses the RZQ pin that is available in every
calibration block in a given I/O bank for series- and parallel-calibrated termination.
The RZQ pin shares the same V
a dual-purpose I/O pin and functions as a GPIO if you do not use the calibration
circuit. When used for OCT calibration, the RZQ pin is connected to GND through an
external 100- or 240-  reference resistor.
All I/O pins support calibrated R
bidirectional pins. Dynamic R
and disabled in transmit mode.
The following connections are required to connect the RZQ pin through a reference
resistor:
■
■
■
■
R
Stratix V devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix V devices support
R
S
S
OCT for single-ended I/O standards (refer to
OCT Without Calibration
RZQ pin is connected to GND through an external 240-  resistor for R
40, 48, 60, and 80 
RZQ pin is connected to GND through an external 240-  resistor for R
30, 40, 60, and 120 
RZQ pin is connected to GND through an external 100-  resistor for R
and 50 
RZQ pin is connected to GND through an external 100-  resistor for R
T
CCIO
OCT is enabled for a bidirectional pin in receive mode
S
OCT and the programmable current strength for the
S
OCT, calibrated R
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
supply with the I/O bank where it is located. It is
T
OCT.
Figure
T
OCT, and dynamic OCT for
5–3).
S
and R
CCIO
T
supply voltage.
OCT in the
S
T
S
S
T
OCT of 25 
OCT,
OCT of 50 
OCT of 34,
OCT of 20,
5–15