DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 244

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–30
Document Revision History
Table 6–7. Document Revision History
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
December 2010
July 2010
Date
Guidelines for DPA-Enabled and DPA-Disabled Differential Channels
The Stratix V device family has differential receivers and transmitters in all I/O
blocks. Each receiver has a dedicated DPA circuit to align the phase of the clock to the
data phase of its associated channel. When you use DPA-enabled channels in
differential banks, you must adhere to the guidelines listed in the following sections.
DPA-Enabled Channels, DPA-Disabled Channels, and Single-Ended I/Os
When you enable a DPA channel in a bank, both single-ended I/Os and differential
I/O standards are allowed in the bank.
Double data rate I/O (DDIO) output pins can be placed within I/O modules that have
the same pad group number as a SERDES differential channel but half rate DDIO
(single data rate) output pins cannot be placed within I/O modules that have the
same pad group number as a receiver SERDES differential channel. The input register
must be implemented within the FPGA fabric logic.
The following lists two DPA restrictions:
■
■
Table 6–7
Version
Because there is only a single DPA clock bus, a PLL drives a continuous series of
DPA channels.
To prevent noise mixing, use one row of separation between two groups of DPA
channels. The two PLLs operate using different reference clocks (either same base
frequency with PPM differences or an entirely different frequencies).
1.2
1.1
1.0
lists the revision history for this chapter.
■
■
■
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Chapter moved to volume 2 for the 11.0 release.
Added
Updated
Updated
Updated
“Differential
“DPA-Enabled Channels, DPA-Disabled Channels, and Single-Ended I/Os”
sections.
Minor text edits.
Table 6–2
Table
Figure 6–2
“Locations of the I/O
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Receiver”,
6–1.
and
and
Table
“Fractional PLLs and Stratix V
Figure
6–3.
Banks”,
6–21.
Changes
“Programmable
Clocking”, and
May 2011 Altera Corporation
Pre-Emphasis”,
Document Revision History