DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 506

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–4
Stratix V Device Handbook Volume 3: Transceivers
Datapath Functionality
The Quartus
10G PCS is enabled. This implies that if you create multiple channels with the 10G
PCS, a common low-speed parallel clock (used in the bonded channel configuration,
such as XAUI) is not generated by the central clock divider block. Each transmitter
channel takes the high-speed clock, generated by the channel PLL, and locally divides
it to generate the parallel clock.
This section discusses the different PCS blocks that you can use in the 10G Low
Latency transceiver configuration.
Transmitter and Receiver FIFO
The FIFOs can be configured in phase compensation or registered mode, as shown in
Figure
in the clock between the read and write side of the FIFO. The clocking scheme for the
write side of the transmitter (TX) and receiver (RX) FIFOs depends on whether the
gear box is enabled, and its ratio (32:64, 40:50, or 40:66). The clocking scheme is
described in the
Figure 5–3. Phase Compensation FIFO in RX Path
Gear Box
The gear box translates the datapath width differences between the PCS and the
physical medium attachment (PMA) interfaces. The gear box contains handshake
control logic and FIFOs to implement the data-width translation. For the supported
gear box ratio, refer to
5–3. In phase compensation mode, the FIFO compensates the phase differences
®
II software only supports the non-bonded configuration (×1) when the
“Clocking”
Transceiver Phase Compensation FIFO
Figure
section.
5–2.
Reg
FIFO
PC
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Reg Mode
Select
rx_clkout
10G Low Latency Configuration
May 2011 Altera Corporation
FPGA Logic