DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 311

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Passive Serial Configuration
Table 9–12. PS Timing Parameters for Stratix V Devices
May 2011 Altera Corporation
t
t
t
t
t
t
t
f
t
t
t
t
t
Notes to
(1) This information is preliminary.
(2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(4) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(5) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
R
F
CD2UM
CD2CU
CD2UMC
Symbol
“Initialization” on page
Table
PS Configuration Using a Download Cable
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–12:
1
1
1
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed configuration data
in the PS configuration scheme.
In this section, the generic term “download cable” includes the Altera USB-Blaster
universal serial bus (USB) port download cable, ByteBlaster II parallel port download
cable, and EthernetBlaster download cable.
In a PS configuration with a download cable, a PC acts as a host to transfer data from
a storage device to the Stratix V device using the download cable. During
configuration, the programming hardware or download cable places the
configuration data one bit at a time on the device’s DATA0 pin. The configuration data
is clocked into the target device until CONF_DONE goes high.
If you turn on the CLKUSR option during PS configuration using a download cable
and the Quartus II programmer, you do not have to provide a clock on the CLKUSR
pin to initialize your device.
9–5.
Parameter
(4)
(Note 1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(Part 2 of 2)
(17,408  CLKUSR
0.45  1/f
0.45  1/f
4 × maximum
DCLK period
period)
Minimum
t
CD2CU
1/f
1,506
175
5.5
—
—
—
2
0
MAX
(5)
MAX
MAX
+
Maximum
125
437
—
—
—
—
—
—
—
40
40
—
—
Units
MHz
s
s
s
ns
ns
ns
ns
—
—
s
s
s
9–31