DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 317

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
JTAG Configuration
Figure 9–23. JTAG Configuration of Multiple Devices Using a Download Cable
Notes to
(1) Connect the pull-up resistor V
(2) If you only use JTAG configuration, connect nCONFIG to V
(3) The resistor value can vary from 1k
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
May 2011 Altera Corporation
Pin 1
convenient on your board. If you are using JTAG in conjunction with another configuration scheme, connect the MSEL[4..0], nCONFIG, and
DCLK based on the selected configuration scheme.
10-Pin Male Header
Download Cable
(JTAG Mode)
Figure
9–23:
V
f
f
CCPD
1
1
V
IO
1 kΩ
(1)
V
CCPD
JTAG-chain device programming is ideal when the system contains multiple devices
or when testing your system using JTAG BST circuitry.
multi-device JTAG configuration.
If you want to use the JTAG multi-device configuration in conjunction with other
schemes, such as a FPP, PS, or AS, tie CONF_DONE, nSTATUS, and nCONFIG together
as recommended in the FPP, PS, or AS multi-device configuration schemes. Ensure
that the JTAG chain is the same order as the multi-device FPP, PS, or AS configuration
chain.
If you only use JTAG configuration, Altera recommends connecting the circuitry as
shown in
isolated to enable each device to enter user mode individually.
For more information about combining the JTAG configuration with other
configuration schemes, refer to the
in volume 2 of the Configuration Handbook.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the Jam player, visit the
(3)
(1)
V
CCPD
AN 425: Using Command-Line Jam STAPL Solution for Device
V
CCPD
(3)
CCPD
(1)
(1)
(2)
(2)
(2)
V
. For more information, refer to V
CCPGM

Figure
10 kΩ
to 10 k
TRST
TDI
nSTATUS
nCONFIG
DCLK
MSEL[4..0]
nCE (4)
TMS
Stratix V Device

9–22, where each of the CONF_DONE and nSTATUS signals are
. Perform signal integrity analysis to select the resistor value for your setup.
CONF_DONE
TCK
TDO
10 kΩ
V
CCPGM
CCPGM
V
CCPD
and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is
(1)
(2)
(2)
(2)
V
CCPD
CCPGM
10 kΩ
Altera
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
requirement in
Combining Different Configuration Schemes
nSTATUS
nCONFIG
DCLK
MSEL[4..0]
nCE (4)
TRST
TDI
TMS
Stratix V Device
CONF_DONE
website.
TCK
“V
TDO
10 kΩ
CCPD
V
CCPGM
V
Pin” on page
CCPD
(1)
(2)
(2)
(2)
Figure 9–23
V
CCPGM
10 kΩ
TRST
TDI
nSTATUS
nCONFIG
DCLK
MSEL[4..0]
nCE (4)
TMS
9–3.
Programming. To
Stratix V Device
CONF_DONE
TCK
shows a
TDO
V
CCPGM
chapter
10 kΩ
9–37