DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 220

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–6
LVDS SERDES
Figure 6–3. LVDS SERDES
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two fractional
(2) In single data rate (SDR) and double data rate (DDR) modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
tx_coreclock
rx_divfwdclk
PLLs are required.
rx_outclock
FPGA
Fabric
Figure
rx_out
tx_in
6–3:
10
10
Figure 6–3
circuitry. This diagram shows the interface signals of the transmitter and receiver
datapath. For more information, refer to
“Differential Receiver” on page
3
(LOAD_EN, diffioclk)
(Note
IOE Supports SDR, DDR, or
2
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
1), (2),
tx_coreclock)
DIN
shows a transmitter and receiver block diagram for the LVDS SERDES
IOE
2
Fractional PLL
2
(3)
3
DOUT
Clock MUX
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
diffioclk
DIN
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
rx_inclock/tx_inclock
6–11.
LVDS Transmitter
LVDS Receiver
DOUT
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
“Differential Transmitter” on page 6–7
DIN
8 Serial LVDS
Clock Phases
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
DPA Clock
Data
DPA Circuitry
DIN
May 2011 Altera Corporation
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
rx_in
tx_out
LVDS SERDES
and