DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 452

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

3–4
Figure 3–2. Transceiver Reset Sequence Timing Diagram for CDR in Automatic Lock Mode
Notes to
(1) t
(2) The rx_is_lockedtodata signal shown in this figure is the logical AND of the rx_is_lockedtodata signals from all channels in a PHY IP
(3) reconfig_busy is driven from the transceiver reconfiguration controller.
Stratix V Device Handbook Volume 3: Transceivers
instance. If one RX channel loses lock, all channels in the PHY IP instance are reset.
pll_powerdown
Figure
Stratix V Device Power Up
(2) rx_is_lockedtodata
rx_is_lockedtodata[1]
rx_is_lockedtodata[2]
rx_is_lockedtodata[0]
3–2:
phy_mgmt_clk_reset
and t
1
Control Signals
reconfig_busy (3)
Status Signals
pll_powerdown
rx_analogreset
LTD
tx_digitalreset
rx_digitalreset
pll_is_locked
are pending characterization.
If you are implementing your own reset controller, follow the same sequence as
shown in the timing diagram
rx_ready
tx_ready
t
pll_powerdown
(1)
clock cycles
(Figure
two parallel
3–2).
Chapter 3: Transceiver Reset Control in Stratix V Devices
t
LTD
(1)
May 2011 Altera Corporation
Transceiver Reset Sequence
t
LTD