DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 409

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
10G PCS Architecture
May 2011 Altera Corporation
Bit-Error Rate (BER) Monitor
The BER monitor block is designed towards the 10GBASE-R protocol specification as
described in 802.3-2008 clause-49. After the block lock is achieved, the BER monitor
starts to count the number of invalid synchronization headers within a 125-s period.
If more than 16 invalid synchronization headers are observed in a 125-s period, the
BER monitor provides the status signal to the FPGA fabric, indicating a high bit error
rate condition.
64B/66B Decoder
The 64B/66B decoder block is designed towards the 10GBASE-R protocol
specification as described in IEEE 802.3-2008 clause-49.
This block contains two sub-blocks:
■
■
The 64B/66B decoder converts the received data from the descrambler into 64-bit data
and 8-bit control characters. The receiver state machine monitors the status signal
from the BER monitor. If it is asserted, the receiver state machine sends local fault
ordered sets to the FPGA interface.
CRC-32 Checker
The CRC-32 checker block is designed to support the Interlaken protocol. The CRC-32
checker calculates the CRC from the incoming data and compares it to the CRC value
sent in the diagnostic word. The CRC error signal is provided to the FPGA fabric.
Figure 1–34
Figure 1–34. CRC-32 Checker
Receiver FIFO
The receiver FIFO block operates in different modes based on the transceiver datapath
configuration, as listed in
Table 1–15. Receiver FIFO Operating Modes for Stratix V Devices
The Quartus II software automatically selects the receiver FIFO mode for the
configuration used.
64B/66B decoder
Receiver state machine
Configuration
10GBASE-R
Interlaken
Data to Receiver FIFO
Custom
shows the CRC-32 checker.
Table
1–15.
Checker
CRC-32
“Phase Compensation Mode”
“Clock Compensation Mode”
Receiver FIFO Mode
Stratix V Device Handbook Volume 3: Transceivers
“Generic Mode”
Data from Frame Synchronizer
1–37