DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 385

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
Figure 1–13. ATX PLL Architecture in Stratix V Devices
May 2011 Altera Corporation
refclk
f
/N
Auxiliary Transmit (ATX) PLL Architecture
Stratix V GX and GS devices contain two ATX PLLs per transceiver block that can
generate the high-speed clocks for the transmitter channels. With these PLLs, you
save the receiver resource that would be used in the channel PLL and used as a
CMU PLL. The ATX PLL has the same building blocks as the other PLLs, as shown in
Figure
full data rate range but they generate less jitter.
As in all PLLs, the VCO operates at half rate and the L-counter dividers, after the
VCO, extends the PLL’s data rate range. The serial clock from the PLL is routed to the
transmitter clock dividers and can be further divided down to half the data rate of the
individual channels. All settings for the PLL and clock dividers are automatically
chosen by the Quartus II software for the best performance based on the data rate and
input clock frequency. Any dedicated reference clocks along the same side of the
device as the ATX PLL can be used to apply the reference input frequency.
For ATX PLL specifications such as input or output frequency ranges, refer to the
and Switching Characteristics for Stratix V Devices
1–13, but are tuned for better performance. ATX PLLs may not operate over the
Frequency
Detector
Phase
Charge
Pump
Loop
Filter
&
/M
VCO
chapter.
Stratix V Device Handbook Volume 3: Transceivers
/L
Serial Clock
DC
1–13