DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 447

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
FPGA Fabric-Transceiver Interface Clocking
May 2011 Altera Corporation
1
To achieve clock resource savings, select a common clock driver for the receiver
datapath interface of all identical receiver channels. This is done by instantiating the
rx_coreclkin port for all the identical receiver channels and connecting the common
clock driver to their receiver datapath interface and receiver data and control logic.
Figure 2–24
(rx_clkout of channel 4). To clock eight identical channels with a single clock,
instantiate the rx_coreclkin port for all the identical receiver channels
(rx_coreclkin[7:0]). Connect rx_clkout[4] to the rx_coreclkin[7:0] ports. Also,
connect rx_clkout[4] to the receiver data and control logic for all eight channels.
Resetting or powering down channel 4 will lead to a loss of the clock for all eight
channels.
Figure 2–24. Eight Identical Channels with a Single User-Selected Receiver Interface Clock
Channel [7:0] Receiver
Data and Control Logic
shows eight identical channels that are clocked by a single clock
FPGA Fabric
rx_coreclkin[7]
rx_coreclkin[6]
rx_coreclkin[5]
rx_coreclkin[4]
rx_coreclkin[2]
rx_coreclkin[1]
rx_coreclkin[0]
rx_coreclkin[3]
rx_clkout[4]
Stratix V Device Handbook Volume 3: Transceivers
Receiver Standard PCS
Channel 7
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
2–31