DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 448

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–32
Document Revision History
Table 2–6. Document Revision History
Stratix V Device Handbook Volume 3: Transceivers
May 2011
December 2010
July 2010
Date
1
Version
The common clock must have a 0 PPM difference with respect to the write side of the
RX FIFO (in the 10G PCS channel) or RX phase compensation FIFO (in the standard
PCS channel) of all the identical channels. A frequency difference causes the FIFO to
under-run or overflow, depending on whether the common clock is faster or slower,
respectively. You can drive the 0 PPM common clock driver by one of the following
sources:
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in the FPGA
logic to drive the rx_coreclkin ports.
Because the Quartus II software allows you to use external pins, such as dedicated
refclk pins, it has no way of ensuring a 0 PPM difference. You must ensure a 0 PPM
difference.
Table 2–6
1.2
1.1
1.0
tx_clkout of any channel in non-bonded receiver channel configurations with the
rate matcher
rx_clkout of any channel in non-bonded receiver channel configurations without
the rate matcher
tx_clkout[0] in bonded receiver channel configurations
Dedicated refclk pins
lists the revision history for this chapter.
■
■
■
■
■
Initial release
Added information about fractional PLLs as they provide an input reference clock in
“Input Reference
Chapter moved to Volume 3.
Updated clock names
Updated figures for more accurate depiction of transceiver clocking
Added information about ATX PLLs
Clocking”.
Changes
Chapter 2: Transceiver Clocking in Stratix V Devices
May 2011 Altera Corporation
Document Revision History