DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 21

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Embedded Memory
Embedded Memory
Variable Precision DSP Block
Table 1–10. Variable Precision DSP Block Configurations
June 2011 Altera Corporation
Multiplier Size (bits)
18×18
27×27
36×36
9×9
Stratix V devices contain two types of embedded memory blocks: MLAB (640-bit) and
M20K (20-Kbit). MLAB blocks are ideal for wide and shallow memories. M20K blocks
are useful for supporting larger memory configurations and include ECC. Both types
operate up to 600 MHz and are configurable to be a single- or dual-port RAM, FIFO,
ROM, or shift register. These memory blocks are flexible and support a number of
memory configurations, as shown in
Table 1–9. Embedded Memory Block Configuration
The Quartus II software simplifies design re-use by automatically mapping memory
blocks from legacy Stratix devices into the Stratix V memory architecture.
Stratix V FPGAs feature the industry’s first variable precision DSP block that you can
configure to natively support signal processing with precision ranging from 9×9 to
36×36.
You can independently configure each DSP block at compile time as either a dual
18×18 multiply accumulate or a single 27×27 multiply accumulate. With a dedicated
64-bit cascade bus, you can cascade multiple variable precision DSP blocks to
implement even higher precision DSP functions efficiently.
different precision is accommodated within a DSP block or by using multiple blocks.
1/3 of Variable Precision DSP Block
1/2 of Variable Precision DSP Block
1 Variable Precision DSP Block
2 Variable Precision DSP Block
DSP Block Resources
MLAB (640 Bits)
32×20
64×10
Table
High precision fixed or single precision floating point
1–9.
Very high precision fixed point
Medium precision fixed point
Low precision fixed point
Expected Usage
M20K (20,480 Bits)
Table 1–10
512×40
1K×20
2K×10
16K×1
4K×5
8K×2
Stratix V Device Handbook
lists how
1–15