DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 164

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–24
Figure 4–20. Dual-Purpose Clock I/O Pins Associated with PLL for Stratix V Devices
Notes to
(1) You can feed these clock output pins using any one of the C[17..0] or m counters. When not used as external clock outputs, these clock output
(2) The FPLL_<#>_CLKOUT0, FPLL_<#>_CLKOUT1, FPLL_<#>_CLKOUT2, and FPLL_<#>_CLKOUT3 pins are single-ended clock output pins.
(3) The FPLL_<#>_CLKOUTp and FPLL_<#>_CLKOUTn pins are differential output pins while the FPLL_<#>_FBp and FPLL_<#>_FBn pins are
(4) The FPLL_<#>_FB0 and FPLL_<#>_FB1 pins are single-ended feedback input pins.
(5) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Fractional PLL0
Fractional PLL1
VCO 0
VCO 1
pins can be used as regular user I/Os.
differential feedback input pins to support differential EFB.
Figure
4–20:
f
1
C10
C11
C12
C13
C14
C15
C16
C17
m0
m1
■
All left and right fractional PLLs in Stratix V devices do not support external clock
outputs except the right fractional PLLs in 5SGSD6 and 5SGSD8devices.
Figure 4–20
Stratix V devices.
Figure 4–20
counter can feed the dedicated external clock outputs. Therefore, one counter or
frequency can drive all output pins available from a given PLL.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in the design into the IOE to implement
the 180° phase with respect to the other pin in the pair. The clock output pin pairs
support the same I/O standards as standard output pins as well as LVDS, LVPECL,
differential high-speed transceiver logic (HSTL), and differential SSTL.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
One differential clock output and one differential feedback input for differential
EFB support (only one of the two adjacent fractional PLLs can support differential
EFB at one time while the other fractional PLL can be used for general-purpose
clocking)
20
shows the dual-purpose clock I/O pins associated with the PLL for
shows that any of the output counters (C[17..0]) on the PLLs or the M
mux
I/O Features in Stratix V Devices
EXTCLKOUT[3..0]
4
EXTCLKOUT[0]
EXTCLKOUT[1]
EXTCLKOUT[2]
EXTCLKOUT[3]
Chapter 4: Clock Networks and PLLs in Stratix V Devices
fbin0
fbin1
chapter.
May 2011 Altera Corporation
IO/FPLL_<#>_CLKOUT0,
FPLL_<#>_CLKOUTp,
FPLL_<#>_FB0
(1), (2), (3), (4)
IO/FPLL_<#>_CLKOUT2,
FPLL_<#>_FBp, FPLL_<#>_FB1
(1), (2), (3), (4)
IO/FPLL_<#>_CLKOUT3,
FPLL_<#>_FBn
(1), (2), (3)
IO/FPLL_<#>_CLKOUT1,
FPLL_<#>_CLKOUTn
(1), (2), (3)
Stratix V PLLs