DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 515

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Standard PCS Custom and Low Latency Configurations
May 2011 Altera Corporation
f
Figure 5–11
interface width. The maximum frequencies shown in
devices.
For more information about the maximum data rate for a certain speed grade, refer to
the
Figure 5–11. Standard PCS Custom 16-Bit PMA-PCS Interface Width
DC and Switching Characteristics for Stratix V Devices
Number of Bonded Channels
Word Aligner (Pattern Length)
Tx Bit Slip
Rate Match FIFO
8B/10B Encoder/Decoder
Byte Serializer/Deserializer
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
Data Rate (Gbps)
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
shows the available options for the standard PCS custom 16-bit PMA-PCS
Stratix V Device Handbook Volume 3: Transceivers
Synchronization State Machine,
Manual Alignment, Automatic
Figure 5–11
Disabled Enabled
Disabled
chapter.
16-Bit
62.5 -
1.0 -
250
4.0
or Bit Slip
Up to ×5
Optional
Disabled
Disabled
Disabled
31.25 -
32-Bit
1.0 -
250
8.0
are for the fastest
5–13