DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 377
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 377 of 530
- Download datasheet (16Mb)
Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
PMA Architecture
May 2011 Altera Corporation
f
Figure 1–6. Full Duplex Channel Showing PMA and PCS Interfaces
The PMA receives and transmits off-chip high-speed serial data streams. You can
configure a PMA channel as a full-duplex channel with a transmitter and receiver or
as a clock multiplier unit (CMU) PLL. Specific CMU PLLs have better performance
with direct clock lines and access to the ×6 clock lines.
For more information, refer to the
The following sections describe the Stratix V PMA architecture:
■
■
The receiver PMA includes the following features:
■
■
■
■
■
■
■
■
“Clock Data Recovery Unit” on page 1–6
“Transmitter PLLs” on page 1–11
“Receiver Input Buffer” on page 1–8
“Programmable Differential On-Chip Termination” on page 1–9
“Programmable V
“Programmable Equalization” on page 1–9
“Signal Threshold Detection Circuitry” on page 1–9
“Offset Cancellation in the Receiver Buffer and Receiver CDR” on page 1–9
“DC Gain” on page 1–10
“Deserializer” on page 1–10
FPGA
Fabric
CM
” on page 1–9
Transmitter PCS
Receiver PCS
Standard PCS
Standard PCS
10G PCS
10G PCS
Transceiver Clocking in Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
Transmitter PMA
Receiver PMA
chapter.
tx_serial_data
rx_serial_data
1–5
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