DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 173

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Document Revision History
Document Revision History
Table 4–5. Document Revision History
May 2011 Altera Corporation
May 2011
December 2010
July 2010
Date
Programmable Duty Cycle
Version
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle
setting is achieved by a low and high time-count setting for the post-scale counters. To
determine the duty cycle choices, the Quartus II software uses the frequency input
and the required multiply or divide rate. The post-scale counter value determines the
precision of the duty cycle. The precision is defined as 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%.
If the PLL is in external feedback mode, set the duty cycle for the counter driving the
fbin pin to 50%. Combining the programmable duty cycle with programmable phase
shift allows the generation of precise non-overlapping clocks.
Table 4–5
1.2
1.1
1.0
■
■
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Chapter moved to volume 2 for the 11.0 release.
Updated
Updated
Figure
Updated
Added
lists the revision history for this chapter.
4–18,
“PLL Clock Outputs”
Table
Figure
“Zero-Delay Buffer Mode”
Figure
4–1.
4–3,
4–20,
Figure
Figure
4–4,
section.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure
4–25, and
and
Changes
4–5,
“External Feedback Mode”
Figure
Figure
4–28.
4–6,
Figure
4–15,
sections.
Figure
4–17,
4–33