DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 320

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–40
Table 9–14. Configuration Pins Description (Part 2 of 3)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CRC_ERROR
CONF_DONE
DATA0
DATA[31..1]
DCLK
DEV_OE
DEV_CLRn
INIT_DONE
Pin Name
(3)
(2)
(2)
(2)
(3)
Optional output pin. Signals that the device has detected a cyclical redundancy check (CRC) error
during user mode operation. this pin is an open-drain output pin by default and requires a 10 k
pull-up resistor. To use this pin as regular output, turn-off the Enable Open-drain on CRC_ERROR pin
in Device and Pins Option, Error Detection CRC panel in the Quartus II software.
The target device drives this pin low if there is no CRC error in user mode operation. As an open-drain
output, if a CRC error occurs, the device releases the pin which is then pulled high by the external
pull-up resistor.
Enable this pin by turning on Enable CRC error detection on CRC_ERROR pin option in the Quartus II
software. For more information about the CRC_ERROR pin, refer to
Devices
Dedicated open-drain bidirectional pin. The target device drives the CONF_DONE pin low before and
during configuration. After all the configuration data is received without error and the initialization
cycle starts, the target device releases the CONF_DONE pin, which is then pulled high by the external
pull-up resistor. The target device then reads the CONF_DONE pin status to ensure that the
CONF_DONE is at logic high. After it is sensed high, the target device initializes and enters user mode.
Driving CONF_DONE low after initialization completes does not affect the configured device.
Dual-purpose data input pin. The data received on DATA0 is synchronized to DCLK.
After configuration completes, this pin is available as a user I/O pin.
Dual-purpose data input pins. If you are using FPP ×16 or FPP ×32, only a subset of these pins are
required for configuration. The pins that are not required for configuration, you can use them as
regular I/Os.
During configuration, byte-wide, or word-wide data is received on these pins. The data received on
DATA[31..1] are synchronized to the DCLK.
Dedicated bidirectional clock pin. In the PS and FPP configurations, DCLK is the clock input used to
clock data from an external source into the target device. Data is latched into the device on the rising
edge of DCLK. After configuration completes, drive DCLK high or low, whichever is more convenient.
In the AS mode, DCLK is an output clock to clock the EPCS or EPCQ devices. Data is latched into the
device on the falling edge of the DCLK. After AS configuration completes, this pin is tri-stated with a
weak pull-up resistor.
Toggling this pin after configuration does not affect the configured device.
Optional input pin that allows you to override all tri-states on the device. When this pin is driven low,
all the I/O pins are tri-stated. When this pin is driven high, all the I/O pins behave as programmed.
Enable this pin by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II
software.
Optional input pin that allows you to override all clears on all the device registers. When this pin is
driven low, all the registers are cleared. When this pin is driven high, all the registers behave as
programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in
the Quartus II software.
Optional output pin. Signals when the device has initialized and is in user mode. During the reset
stage, after the device exits POR, and during the beginning of the configuration, the INIT_DONE pin
is tri-stated and pulled high due to an external pull-up resistor.
After the option bit to enable INIT_DONE is programmed into the device (during the first frame of
configuration data), the INIT_DONE pin goes low. When initialization completes, the INIT_DONE
pin is released and pulled high and the device enters user mode.
Thus, the monitoring circuitry must be able to detect a low-to-high transition. Enable this pin by
turning on the Enable INIT_DONE output option in the Quartus II software.
chapter.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Description
SEU Mitigation in Stratix V
May 2011 Altera Corporation
Device Configuration Pins
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