DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 420

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–4
Internal Clocking
Stratix V Device Handbook Volume 3: Transceivers
Fractional PLLs
Stratix V devices provide a fractional PLL for each group of three transceiver
channels. Each fractional PLL drives one of two clock lines spanning the side of the
device that can provide a clock to any transmit PLL or CDR on the same side of the
device. A fractional PLL enables you to use an input reference clock in your system
that is not supported by the transmit PLL or CDR to synthesize a supported input
reference clock required by the transmit PLL or CDR. For the Quartus II software 11.0,
only the integer mode is supported. Integer mode allows you to synthesize clocks that
are integer multiples or factors of itself. For example, if you have a 10 MHz clock
available, you can synthesize a clock of 5, 20, and 30 MHz.
Figure 2–4
Figure 2–4. Fractional PLL Input Clock Sources
Note to
(1) A fractional PLL can provide a clock source to another fractional PLL through the reference clock lines driven by the
This section describes the clocking architecture internal to Stratix V transceivers.
Different physical coding sublayer (PCS) configurations and channel bonding options
result in various transceiver clock paths.
the transceiver internal clocking:
■
■
■
“Transmitter Clock Network”
“Transmitter Clocking”
“Receiver Clocking”
fractional PLLs.
Dedicated
Figure 2–4
refclk
pin
shows the input clock sources for the fractional PLL.
:
Reference Clock
Network
(C in
(B in
Figure
Fractional
PLL (1)
Figure
(A in
2–5)
Figure
2–5)
Figure 2–5
Chapter 2: Transceiver Clocking in Stratix V Devices
2–5)
Clock
Input
shows the following sections of
Fractional
PLL
May 2011 Altera Corporation
Input Reference
Transmit PLL
Clock to the
or CDR
Internal Clocking