DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 276

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

8–2
Hot-Socketing Feature Implementation in Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
I/O Pins Remain Tri-Stated During Power Up
Insertion or Removal of a Stratix V Device from a Powered-Up System
A device that does not support hot socketing can interrupt the system operation or
cause contention by driving out before or during power up. In a hot-socketing
situation, the Stratix V output buffers are turned off during system power up or
power down. Also, the Stratix V device does not drive out until the device is
configured and working within the recommended operating conditions.
When powered up through the device signal pins, devices that do not support hot
socketing are directly connected to the GND, causing power supplies failure. This
irregular power up can damage both the driving and driven devices and can disrupt
card power up.
You can insert a Stratix V device into or remove it from a powered-up system board
without damaging the system board or interfering with its operation.
The hotsocket circuit monitors the V
power supplies can be powered up or powered down in any sequence. During hot
socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is
less than 20 pF.
You must ensure that all power supplies for Stratix V devices are within the ramp-up
and ramp-down rate of 200 µs to 100 ms.
A possible concern regarding hot socketing is the potential for “latch up”. When hot
socketing, Stratix V devices are immune to latch up. Latch up occurs when electrical
subsystems are hot socketed into an active system. During hot socketing, the signal
pins can be connected and driven by the active system before the power supply can
provide current to the power and GND planes of the device. This condition can lead
to latch up and cause a low-impedance path from power to GND within the device.
As a result, the device draws a large amount of current, possibly causing electrical
damage.
The hot-socketing feature turns off the output buffer during power up and power
down of the V
V
generates an internal HOTSCKT signal. Hot-socketing circuitry is designed to prevent
excess I/O leakage during power up. When the voltage ramps up very slowly, it is
still relatively low, even after the POR signal is released and the configuration is
completed. The CONF_DONE and nSTATUS pins fail to respond, as the output buffer
cannot flip from the state set by the hot-socketing circuit at this low voltage.
Therefore, the hot-socketing circuitry is removed from these configuration pins to
ensure that they can operate during configuration. Thus, it is an expected behavior for
these pins to drive out during power-up and power-down sequences.
CC
power supplies are below the threshold voltage, the hot-socketing circuitry
CCIO
, V
CCPD
, and V
CC
Chapter 8: Hot Socketing and Power-On Reset in Stratix V Devices
CCIO
power supplies. When the V
, V
CCPD
Hot-Socketing Feature Implementation in Stratix V Devices
, and V
CC
power supplies. These
May 2011 Altera Corporation
CCIO
, V
CCPD
, and