DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 294

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–14
Table 9–7. FPP Timing Parameters for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
Notes to
(1) This information is preliminary.
(2) Use these timing parameters when the decompression and design security features are disabled.
(3) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(4) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(6) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
R
F
CD2UM
CD2CU
CD2UMC
“Initialization” on page
Table
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency (FPP 8/16)
DCLK frequency (FPP 32)
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–7:
Table 9–7
the DCLK-to-DATA[] ratio is 1.
9–5.
lists the timing parameters for Stratix V devices for FPP configuration when
Parameter
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
(5)
(Note
1),
(2)
(17,408  CLKUSR
4 × maximum
0.45  1/f
0.45  1/f
DCLK period
period)
Minimum
t
CD2CU
1/f
1,506
268
175
5.5
—
—
—
—
—
—
—
2
2
0
MAX
(6)
MAX
MAX
+
Fast Passive Parallel Configuration
May 2011 Altera Corporation
Maximum
1,506
1,506
600
600
125
100
437
—
—
—
—
—
—
—
—
40
40
—
—
(3)
(4)
Units
MHz
MHz
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
—
—
s
s
s