DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 404

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–32
Figure 1–28. 8B/10B Encoder Output During reset_tx_digital Assertion
10G PCS Architecture
Table 1–13. Configurations Supported in 10G PCS for Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
Transceiver Configuration
reset_tx_digital
dataout[9:0]
10G Custom
10GBASE-R
Interlaken
clock
1
K28.5-
Reset Condition
The reset_tx_digital signal resets the 8B/10B encoder. During reset, running
disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5
pattern from the RD- column continuously until reset_tx_digital is de-asserted.
The input data and control code from the FPGA fabric is ignored during the reset
state. After reset, the 8B/10B encoder starts with a negative disparity (RD-) and
transmits three K28.5 code groups for synchronization before it starts encoding and
transmitting the data on its output.
While reset_tx_digital is asserted, the downstream 8B/10B decoder that receives
the data might observe synchronization or disparity errors.
Figure 1–28
(reset_tx_digital is high), a K28.5- (K28.5 10-bit code group from the RD-column) is
sent continuously until reset_tx_digital is low. Because of some pipelining of the
transmitter channel PCS, some “don’t cares” (10’hxxx) are sent before the three
synchronizing K28.5 code groups. User data follows the third K28.5 code group.
The 10G PCS offers a full duplex (transmitter and receiver) transceiver channel that
supports serial data rates from 2.0 to 12.5 Gbps.
Several of the functional blocks are customized for protocols such as Interlaken or
10GBASE-R. The different datapath configurations for these protocols are available
through the different ALT PHY MegaWizard
Table
1–13.
K28.5-
shows the reset behavior of the 8B/10B encoder. When in reset
Transceiver ALT PHY IP
Low Latency PHY IP
K28.5-
10GBASE-R PHY IP
Interlaken PHY IP
XXX
Data Rate (Gbps)
3.125 to 10.3125
XXX
2.0 to 12.5
Chapter 1: Transceiver Architecture in Stratix V Devices
10.3125
™
Plug-In Managers, as shown in
K28.5-
K28.5+
10GBASE-R
Transceiver Protocol
Configurations in Stratix V
Devices chapter
Interlaken
Protocol Configurations in
Stratix V Devices chapter
10G Low Latency
Configuration
Transceiver Custom
Configurations in Stratix V
Devices chapter
May 2011 Altera Corporation
K28.5-
Refer to
in the Transceiver
10G PCS Architecture
in the
in the
Dx.y+