DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 18

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–12
Table 1–7. Transceiver PCS Features (Part 2 of 2)
PCIe Gen 3/2/1 Hard IP (Embedded HardCopy Block)
Stratix V Device Handbook
×1, ×4, ×8 PCIe
Gen3
10G Ethernet
Interlaken
40GBASE-R
Ethernet
100GBASE-R
Ethernet
OTN 40 and 100
GbE
XAUI
SRIO
CPRI
GPON
Protocol
Data Rates (Gbps)
Stratix V devices have PCIe hard IP designed for performance, ease-of-use, and
increased functionality. The PCIe hard IP consists of the PCS, data link, and
transaction layers. It supports Gen 3/2/1 end point and root port up to ×8 lane
configurations.
The Stratix V PCIe hard IP operates independently from the core logic, which allows
the PCIe link to wake up and complete link training in less than 100 ms while the
Stratix V device completes loading the programming file for the rest of the FPGA. It
also provides added functionality, which makes it easier to support emerging features
such as Single Root I/O Virtualization (SR-IOV) or optional protocol extensions. In
addition, the Stratix V device PCIe hard IP has improved end-to-end data path
protection using ECC and enables device Configuration via Protocol.
4.9 to 10.3125
0.6144 to 9.83
(10 +1) × 11.3
10 × 10.3125
3.125 to 4.25
(4 +1) × 11.3
1.25 and 2.5
1.25 to 6.25
4 × 10.3125
10.3125
1.25
8
Phase compensation FIFO, encoder,
scrambler, gear box, and bit slip
TX FIFO, 64/66 encoder, scrambler,
and gear box
TX FIFO, frame generator, CRC-32
generator, scrambler, disparity
generator, and gear box
TX FIFO, 64/66 encoder, scrambler,
alignment marker insertion, gearbox,
and block striper
TX FIFO, channel bonding, and byte
serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for bonding four channels
Same as custom PHY plus SRIO V2.1
compliant ×2 and ×4 channel bonding
Same as Custom PHY plus TX
deterministic latency
Same as custom PHY
Transmit Data Path
PCIe Gen 3/2/1 Hard IP (Embedded HardCopy Block)
Chapter 1: Stratix V Device Family Overview
Block synchronization, rate match
FIFO, decoder, de-scrambler, and
phase compensation FIFO
RX FIFO, 64/66 decoder,
de-scrambler, block synchronization,
and gear box
RX FIFO, frame generator, CRC-32
checker, frame decoder, descrambler,
disparity checker, block
synchronization, and gearbox
RX FIFO, 64/66 decoder,
de-scrambler, lane reorder, deskew,
alignment marker lock, block
synchronization, gear box, and
destripper
RX FIFO, lane deskew, and byte
de-serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for re-aligning four channels
Same as custom PHY plus SRIO
V2.1-compliant ×2 and ×4 deskew
state machine
Same as Custom PHY plus RX
deterministic latency
Same as custom PHY
Receiver Data Path
June 2011 Altera Corporation