DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 384

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–12
Figure 1–12. CMU PLL in Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
rx_serial_data
signal detect
refclk
f
f
Channel PLL
Channel PLL Used as a CMU PLL (Transmitter PLL)
As stated previously, each channel PLL can function as a CMU PLL or a CDR PLL.
This section describes the CMU PLL.
When you use the channel PLL as the CMU PLL, the receiver channel is not available
as a receiver, but the transmitter in that channel is still available. The channel PLL is in
LTR mode only.
The PLL’s VCO operates at half rate and the L-counter dividers, after the VCO, extend
the PLL’s data rate range. The serial clock from the PLL is routed to the transmitter
clock dividers and can be further divided down to half the data rate of the individual
channels. All settings for the PLL and clock dividers are automatically chosen by the
Quartus II software for the best performance based on the data rate and input clock
frequency.
For CMU PLL specifications such as input or output frequency ranges, refer to the
and Switching Characteristics for Stratix V Devices
Figure 1–12
For more information, refer to the
/N
shows the portion of a channel PLL that functions as a CMU PLL.
/2 /2
Controller
Controller
Frequency
Detector
LTR/LTD
LTR/LTD
Detector
Detector
Phase
Phase
Phase
(PFD)
(PD)
(PD)
Up
Down
Down
Down
Up
Up
Transceiver Clocking in Stratix V Devices
Charge Pump
Loop Filter
&
Chapter 1: Transceiver Architecture in Stratix V Devices
chapter.
Controlled
Oscillator
Voltage
Detect
(VCO)
Lock
/M
/ 2 / 2
May 2011 Altera Corporation
/L
PMA Architecture
chapter.
Recovered Clock
Serial Clock
pll_is_locked
DC