DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 83

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
Adaptive Logic Modules
Figure 1–5. High-Level Block Diagram of the Stratix V ALM
May 2011 Altera Corporation
datae0
datae1
dataf0
dataf1
dataa
datab
datac
datad
In addition to the adaptive LUT-based resources, each ALM contains four
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can efficiently
implement various arithmetic functions and shift registers. Each ALM drives all types
of interconnects: local, row, column, carry chain, shared arithmetic chain, register
chain, and direct link.
ALM.
Combinational/Memory ALUT1
Combinational/Memory ALUT0
shared_arith_out
shared_arith_in
6-Input LUT
6-Input LUT
carry_in
carry_out
adder0
adder1
Figure 1–5
shows a high-level block diagram of the Stratix V
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
reg_chain_in
reg_chain_out
labclk
D
D
D
D
reg0
reg1
reg2
reg3
Q
Q
Q
Q
To general or
To general or
To general or
To general or
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
local routing
local routing
local routing
local routing
1–5