DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 335

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Design Security
Table 9–19. Security Key Types
May 2011 Altera Corporation
Volatile Key
Non-volatile Key
Notes to
(1) V
(2) In-socket programming is offered through third party vendors.
continuously supplies power to the volatile register regardless of the on-chip supply condition.
CCBAT
Key Types
Table
JTAG Secure Mode
Security Key Types
is a dedicated power supply for volatile key storage and not shared with other on-chip power supplies, such as V
9–19:
f
f
f
1
When you enable tamper-protection bit, Stratix V devices are in JTAG secure mode
after power-up. During JTAG secure mode, many JTAG instructions are disabled.
Stratix V devices only allow mandatory JTAG 1149.1 and 1149.6 instructions to be
exercised. These instructions are SAMPLE/PRELOAD, BYPASS, EXTEST, and optional
instructions such as IDCODE and SHIFT_EDERROR_REG.
To enable the access of other JTAG instructions such as USERCODE, HIGHZ, CLAMP,
PULSE_NCONFIG, and CONFIG_IO, you must issue UNLOCK instruction to deactivate the
JTAG secure mode. You can issue LOCK instruction to put the device back into JTAG
secure mode. Both the LOCK and UNLOCK instructions can only be issued during user
mode.
For more information about JTAG binary instruction code related to the LOCK and
UNLOCK instructions, refer to the
chapter.
Stratix V devices offer two types of keys—volatile and non-volatile.
the differences between the volatile key and non-volatile key.
Both non-volatile and volatile key programming offers protection from reverse
engineering and copying. If you set the tamper-protection bit, the design is also
protected from tampering.
Perform key programming through the JTAG interface. Also, ensure that the
nSTATUS pin is released high before any key-programming attempts.
For more information about battery specifications, refer to the
Characteristics for Stratix V Devices
For more information about the V
Stratix V Device Family Pin Connection
■
■
One-time programming
Re-programmable
Erasable
Key Programmability
Required external battery,
V
Does not require an external
battery
Power Supply for Key Storage
CCBAT
JTAG Boundary-Scan Testing in Stratix V Devices
CCBAT
chapter.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(1)
Guidelines.
pin connection recommendations, refer to the
On-board
On-board and in-socket
programming
Programming Method
DC and Switching
Table 9–19
CCIO
(2)
or V
CCPGM
. V
lists
CCBAT
9–55