DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 271

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
Table 7–7. I/O Configuration Block Bit Sequence
Table 7–8. DQS Configuration Block Bit Sequence (Part 1 of 2)
May 2011 Altera Corporation
0..5
6..11
12..17
18..23
24..25
26..27
28
29..32
0..5
6..11
12..17
18..23
24..25
26
27
28..29
30
31
32..33
34
35
36
37..38
39
40
41..42
43
44
45
46..47
48
49
50..51
Bit
Bit
Table 7–7
Table 7–8
lists the I/O configuration block bit sequence.
lists the DQS configuration block bit sequence.
padtoinputregisterrisefalldelaysetting[0..5]
padtoinputregisterdelaysetting[0..5]
resyncinputphasesetting[0..1]
dqs2xoutputphasesetting[0..1]
dqsbusoutdelaysetting2[0..5]
dq2xoutputphasesetting[0..1]
inputclkndelaysetting[0..1]
dutycycledelaysetting[0..3]
dqsbusoutdelaysetting[0..5]
dqsoutputphasesetting[0..1]
postamblephasesetting[0..1]
inputclkdelaysetting[0..1]
dqoutputphasesetting[0..1]
outputdelaysetting1[0..5]
outputdelaysetting2[0..5]
octdelaysetting1[0..5]
octdelaysetting2[0..5]
addrphasesetting[0..1]
resyncinputphaseinvert
dqs2xoutputphaseinvert
dqsoutputphaseinvert
resyncinputpowerdown
postamblephaseinvert
dqs2xoutputpowerdown
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
dqoutputphaseinvert
dutycycledelaymode
dqsoutputpowerdown
postamblepowerdown
dqoutputpowerdown
addrphaseinvert
addrpowerdown
Bit Name
Bit Name
—
—
7–27