DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 169

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
Figure 4–25. ZDB Mode in Stratix V PLLs
Note to
(1) ZDB mode can support up to four single-ended clock outputs. For more information, refer to
May 2011 Altera Corporation
Figure
inclk
inclk
4–25:
1
1
÷n
÷n
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin
for zero delay through the device. When using this mode, you must use the same I/O
standard on the input clocks and output clocks to guarantee clock alignment at the
input and output pins. ZDB mode is supported only on the center and corner PLLs in
Stratix V devices.
When using Stratix V PLLs in ZDB mode, along with single-ended I/O standards, to
ensure phase alignment between the CLK pin and the external clock output (CLKOUT)
pin, you must instantiate a bi-directional I/O pin in the design to serve as the
feedback path connecting the FBOUT and FBIN ports of the PLL. The PLL uses this
bidirectional I/O pin to mimic, and compensate for, the output delay from the clock
output port of the PLL to the external clock output pin.
The bidirectional I/O pin that you instantiate in your design must always be assigned
a single-ended I/O standard.
To avoid signal reflection when using ZDB mode, do not place board traces on the
bi-directional I/O pin.
Figure 4–25
use differential I/O standards on the PLL clock input or output pins.
PFD
PFD
CP/LF
CP/LF
shows ZDB mode in Stratix V PLLs. When using ZDB mode, you cannot
(Note 1)
VCO 0
VCO 1
C10
C11
C12
C13
C14
C15
C16
C17
m0
m1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
20
mux
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4
EXTCLKOUT[0]
EXTCLKOUT[1]
EXTCLKOUT[2]
EXTCLKOUT[3]
Figure 4–20 on page
fbout0
fbin0
fbout1
fbin1
4–24.
bidirectional I/O pin
bidirectional I/O pin
4–29