DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 17

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Stratix V Device Family Overview
Low-Power Serial Transceivers
Table 1–6. Transceiver PMA Features
Table 1–7. Transceiver PCS Features (Part 1 of 2)
June 2011 Altera Corporation
Backplane support
Cable driving support
Optical module support with EDC
Chip-to-chip support
Continuous Time Linear Equalization
(CTLE)
Decision Feedback Equalization (DFE)
Adaptive equalization (ADCE)
PLL-based clock recovery
Programmable deserialization and word
alignment
Transmit equalization (pre-emphasis)
Ring and logic cell oscillator transmit
PLLs
On-chip instrumentation (EyeQ data-eye
monitor)
Dynamic reconfiguration
Protocol support
Custom PHY
Custom 10G PHY
×1, ×4, ×8 PCIe
Gen 1/2
Protocol
Features
Data Rates (Gbps)
Table 1–6
The Stratix V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or
66-bit interface, depending on the transceiver data rate and protocol. Stratix V devices
contain PCS hard IP to support PCIe Gen 3/2/1, 40G/100G Ethernet, Interlaken,
10GE, XAUI, GbE, SRIO, CPRI, and GPON protocols. All other standard and
proprietary protocols are supported through the transceiver PCS hard IP.
lists the transceiver PCS features.
9.98 to 14.1
2.5 and 5.0
0.6 to 8.5
lists the PMA features for the Stratix V transceivers.
Receiver 5-tap digital equalizer to minimize losses and crosstalk
10GBASE-R, 14.1 Gbps (Stratix V GX/GS devices), 12.5 Gbps (Stratix V GT
devices)
PCIe cable and eSATA applications
10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad
Small Form-factor Pluggable (QSFP), CXP, 100G Pluggable (CFP), 100G
Form-factor Pluggable
28 Gbps and 12.5 Gbps (Stratix V GT devices) and 14.1 Gbps (Stratix V GX/GS
devices)
Receiver 4-stage linear equalization to support high-attenuation channels
Adaptive engine to automatically adjust equalization to compensate for changes
over time
Superior jitter tolerance versus phase interpolation techniques
Flexible deserialization width and configurable word alignment patterns
Transmit driver 4-tap pre-emphasis and de-emphasis for protocol compliance
under lossy conditions
Choice of transmit PLLs per channel, optimized for specific protocols and
applications
Allows non-intrusive on-chip monitoring of both width and height of the data
eye
Allows reconfiguration of single channels without affecting operation of other
channels
Compliance with over 50 industry standard protocols in the range of 600 Mbps
to 28 Gbps
Phase compensation FIFO, byte
serializer, 8B/10B encoder, bit-slip,
and channel bonding
TX FIFO, gear box, and bit-slip
Same as custom PHY plus PIPE 2.0
interface to core logic
Transmit Data Path
Capability
Word aligner, de-skew FIFO, rate
match FIFO, 8B/10B decoder, byte
deserializer, and byte ordering
RX FIFO and gear box
Same as custom PHY plus PIPE 2.0
interface to core logic
Receiver Data Path
Stratix V Device Handbook
Table 1–7
1–11