DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 450

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

3–2
Figure 3–1. PHY IP Instance with Embedded Reset Sequence Controller
Table 3–2. Reset Control and Status Signals
Stratix V Device Handbook Volume 3: Transceivers
phy_mgmt_clk_reset
phy_mgmt_clk
phy_mgmt_clk_reset
tx_ready
rx_ready
phy_mgmt_clk
Signal Name
Transceiver PHY
Avalon-MM
Interface
Figure 3–1
reset sequence controller.
Table 3–2
Status Output
Status Output
Control Input
Control Input
Signal Type
PHY Management
S
Receiver
PCS
Avalon-MM
lists the reset control and status signals provided to the user logic.
shows a block diagram of the PHY IP core instance with the embedded
rx_digitalreset
tx_digitalreset
M
reconfig_from_xcvr
Transmitter
Clock for the reset controller
Low-to-high transition initiates the transceiver reset sequence
Low indicates that the TX datapath is in reset. High indicates that the TX
datapath is out of reset and ready for data transmission.
Low indicates that the RX datapath is in reset. High indicates that the RX
datapath is out of reset and ready for data reception.
PCS
PCS and PMA Control
and Status Register
rx_is_lockedtodata
Reset Controller
Reconfiguration
Memory Map
Transceiver
Controller
S
reconfig_to_xcvr
Receiver
PMA
CDR
rx_analogreset
Chapter 3: Transceiver Reset Control in Stratix V Devices
pll_is_locked
reconfig_busy
Description
Transmitter
Transmitter
PMA
PLL
Transceiver Reset Controller Implementation
pll_powerdown
May 2011 Altera Corporation
tx_ready
rx_ready
user logic
to / from