DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 163

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
Figure 4–19. Fractional PLL High-Level Block Diagram
Notes to
(1) This is the VCO post-scale counter K.
(2) Only C0, C2, C15, and C17 can drive the TX serial clock and C1, C3, C14, and C16 can drive the TX load enable.
(3) This FBOUT port is fed by the M counter in the Stratix V PLLs.
May 2011 Altera Corporation
from adjacent PLL
Cascade input
GCLK/RCLK
clock inputs
Dedicated
pfdena
Figure
Fractional PLL Architecture
PLL External Clock I/O Pins
4–19:
4
Figure 4–19
Fractional PLL Usage
You can configure the fractional PLL as either an integer or an enhanced fractional
mode. One fractional PLL can use up to 18 output counters and all external clock
outputs. Two adjacent fractional PLLs share the 18 output counters.
You can use fractional PLLs to reduce the number of oscillators required on the board,
as well as to reduce the clock pins used in the FPGA by synthesizing multiple clock
frequencies from a single reference clock source. In addition, you can use fractional
PLLs for clock network delay compensation, zero-delay buffering, and transmit
clocking for transceivers.
Two adjacent corner and center fractional PLLs share four dual-purpose clock I/O
pins, organized as one of the following combinations:
■
■
■
■
inclk0
inclk1
Four single-ended clock outputs
Two single-ended outputs and one differential clock output
Four single-ended clock outputs and two single-ended feedback inputs within the
I/O driver feedback for ZDB support
Two single-ended clock outputs and two single-ended feedback inputs for
single-ended External Feedback (EFB) support
Switchover
Clock
Block
shows the high-level block diagram of the Stratix V fractional PLL.
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
Circuit
Lock
CP
Delta Sigma
Modulator
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
locked
LF
VCO
8
Direct compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(1)
To DPA block
÷
2,
8
÷
4
8
÷C17
÷C0
÷C1
÷C2
÷C3
÷m
FBIN
DIFFIOCLK network
GCLK/RCLK network
Casade output
to adjacent PLL
GCLKs
RCLKs
External clock
outputs
TX serial clock (2)
TX load enable (2)
FBOUT (3)
External memory
interface DLL
PMA clocks
4–23